Stacked chip device

ABSTRACT

The present disclosure relates to a stacked chip device including a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions, a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns, and a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns, wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No.10-2014-0011099 filed on Jan. 29, 2014 and all the benefits accruingtherefrom under 35 U.S.C. §119, the contents of which are incorporatedby reference in their entirety.

BACKGROUND

The present disclosure relates to a stacked chip device in which unitdevices having different characteristics are combined to a single chip,and more particularly, to a stacked chip device undirected and havingensured reliability.

In an electronic device, representative passive devices include aresistor R, a capacitor C, and an inductor L, and functions and roles ofthese passive devices are various. For example, a resistor controls flowof a current flowing through a circuit and also plays a role ofachieving impedance matching in an alternating current circuit. Acapacitor basically plays a role of blocking a direct current andtransmitting an alternating current signal, configures a time constantcircuit, a delay circuit, an RC circuit, and an LC filter circuit, andremoves noise for itself. An inductor performs functions of removinghigh frequency noise, and impedance matching.

In addition, due to varied resistance according to an applied voltage, avaristor device is widely used as a protection device for protectingimportant electronic components and circuits from overvoltage (a surgevoltage) and static electricity. In other words, even though a currentdoes not flow through a varistor device disposed inside a circuit, whenovervoltage not smaller than a certain voltage or overvoltage due tolightening is applied on both terminals of the varistor, resistance ofthe varistor device rapidly decreases, almost all current flows throughthe varistor device and no current flows through other devices, andtherefore the circuit is protected from the overvoltage. Such varistordevices are recently in a trend of being miniaturized and arrayed inorder to protect a large-scale integrated circuit or the like fromstatic electricity and overvoltage in response to miniaturization ofelectronic devices.

For example, important electronic components or circuits may beefficiently protected from overvoltage by combining the varistor deviceand a resistor device, and stable operation of the electronic componentsor circuits can be ensured by combining the varistor device and aninductor device to remove a noise component.

In such a way, when various unit devices are combined to one chip, aplurality of sheets are stacked in a vertical direction to manufacture achip and conduction patterns including electrodes for realizing eachdevice are formed on each sheet. At this point, a stacked chip devicebecomes to have directivity according to a horizontal arrangement or avertical stack arrangement of unit devices. In other words, the stackedchip has directivity of different characteristics in the horizontaldirection or the vertical direction. In this case, the stacked chip isrequired to be used in correspondence to the directivity when used in anelectronic circuit, and a direction recognition mark is required to beindicated so that the directivity can be distinguished at the time ofmanufacturing the stacked chip. Accordingly, a manufacturing processbecomes complex, caution is necessary in use thereof, and mounting taskis delayed.

In addition, in the stacked chip device, a through-hole is formed whichpenetrates the conduction pattern on each sheet, and the conductionpatterns are connected in a vertical direction by filling thethrough-hole with a conductor. At this point, since the chip ismanufactured by stacking and compressing the plurality of sheets, stressis accumulated on a region where a through-hole is disposed, inparticular, on a region where the through-hole is disposed in anoverlapped manner, the conductor in the through-hole is modified, and adistance to a conduction pattern adjacent thereto becomes nearer thanthat originally designed. Accordingly, design characteristics of thestacked chip device are not properly realized. When the conductor in thethrough-hole becomes severely modified, electricity is partiallyconcentrated to be short-circuited, to cause a leakage current, or tocreate a transient current.

Patent Literature 1: Korean Patent Laid-Open Publication No.10-2011-0049200

SUMMARY

The present disclosure provides a stacked chip device undirected andexcellent in usability.

The present disclosure also provide a stacked chip device capable ofrestricting or preventing a leakage current or a transient current, andensuring reliability.

In accordance with an exemplary embodiment, a stacked chip deviceincludes: a first stack unit comprising a plurality of electrodepatterns respectively disposed for a unit device region and commonelectrode patterns formed to be connected to cross the unit deviceregions; a second stack unit disposed on a top portion of the firststack unit and comprising a plurality of first conductor patterns; and athird stack unit disposed on a bottom portion of the first stack unitand comprising a plurality of second conductor patterns, wherein thefirst and second conductor patterns are formed on a plurality of sheets,the first and second conductor patterns formed on one sheet are formedacross a plurality of unit device regions, and the first and secondconductor patterns are connected vertically through vias formedpenetrating through at least some of the sheets.

The first and second conductor patterns may be formed on one sheet tocross at least two unit devices, the vias may include first central viasformed on central portions of the first conductor patterns, first endportion vias formed on end portions of the first conductor patterns,second central vias formed on central portions of the second conductorpatterns, and second end portions via formed on end portions of thesecond conductor patterns, central axes of the first and second centralvias may be separated from each other, and the first and second endportion vias may be separately disposed in a horizontal direction.

The first central vias and the first end portion vias may be formedalternately in a vertical direction, and the second central vias and thesecond end portion vias may be formed alternately in the verticaldirection.

The stacked chip device may further include a plurality of firstexternal terminals configured to be connected to parts of the pluralityof electrode patterns and the plurality of first conductor patterns; aplurality of second external terminals configured to be connected to aremaining part of the plurality of electrode patterns and the pluralityof second conductor patterns; and common external terminals connected tothe common electrode patterns. The first and second external terminalsare disposed alternately.

A width of one exposed end portion of the plurality of electrodepatterns may be narrower than that of another end portion, and at leastone of the end portions of the plurality of electrode patterns may bedeviated from a central line configured to divide the electrode patternsinto two parts.

The common electrode patterns may include non-conductor regions on atleast parts of portions facing the vias.

In accordance with another exemplary embodiment, a stacked chip deviceincludes: a first stack unit comprising a plurality of electrodepatterns respectively disposed for a unit device region and commonelectrode patterns formed to be connected to cross the unit deviceregions; and conductor stack unit configured to be disposed on at leastone side of a top portion and a bottom portion of the first stack unitand comprising a plurality of conductor patterns, wherein the conductorpatterns are formed on a plurality of sheets and connected verticallythrough vias formed penetrating through at least some of sheets, and thecommon electrode patterns comprises non-conductor regions on at leastparts of portions facing the vias.

The conductor stack units may include a second stack unit disposed on atop portion of the first stack unit and including a plurality of firstconductor patterns; and a third stack unit disposed on a bottom portionof the first stack unit and including a plurality of second conductorpatterns, wherein at least one of the first and second conductorpatterns are formed on the plurality of sheets, and at least one of thefirst and second patterns are connected vertically through vias formedpenetrating through at least some of sheets.

The common electrode patterns may include a top common electrode patternformed on a top portion of the electrode patterns and a bottom commonelectrode pattern formed on a bottom portion of the electrode patterns,the top common electrode pattern may include a non-conductor region on aportion facing a first via configured to connect the first conductorpattern vertically, and the bottom common electrode pattern may includea non-conductor region on a portion facing a second via configured toconnect the second conductor pattern vertically.

The common electrode patterns may include a top common electrode patternformed on a top portion of the electrode patterns and a bottom commonelectrode pattern formed on a bottom portion of the electrode patterns,and the top common electrode pattern and the bottom common electrodepattern may include non-conductor regions on a portion facing a firstvia configured to connect the first conductor patterns vertically and ona portion facing a second via configured to connect the second conductorpatterns vertically.

The first vias may include first central vias formed at central portionsof the first conductor patterns and first end portion vias formed at endportions of the first conductor patterns, the second vias may includesecond central vias formed at central portions of the second conductorpatterns and second end portion vias formed at end portions of thesecond conductor patterns, and the first and second end portion vias maybe separately disposed at different positions in a horizontal direction.

The electrode patterns may include non-conductor regions on at leastparts of portions facing the vias.

The common electrode patterns may be formed on a sheet, and thenon-conductor regions may include regions in which parts of the commonelectrode patterns are removed and the sheet is exposed. In addition,the non-conductor regions comprise insulation layers configured to coverparts of the common electrode patterns. Furthermore, the non-conductorregions may be formed with a size that is the same as or greater thanthat of the vias.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments can be understood in more detail from thefollowing description taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is an exploded perspective view and appearances schematicallyillustrating a stacked chip device in accordance with an exemplaryembodiment;

FIG. 2 is a conceptual cross-sectional view for explaining an internalpattern of the device of FIG. 1;

FIG. 3 is an equivalent circuit diagram of a unit device in the deviceof FIG. 1;

FIG. 4 is an exploded perspective view and appearance schematicallyillustrating a stacked chip device in accordance with another exemplaryembodiment;

FIG. 5 is an exploded perspective view illustrating in detail the firststack unit of the device of FIG. 4;

FIGS. 6 and 7 are exploded perspective views illustrating in detail thefirst stack unit of the stacked chip device according to a modificationexample of the exemplary embodiment; and

FIG. 8 is a cross-sectional view illustrating in detail a non-conductorregion in the stacked chip device according to an modification exampleof the exemplary embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, specific embodiments will be described in detail withreference to the accompanying drawings. The present invention may,however, be embodied in different forms and should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the present invention to those skilled inthe art. In the figures, the dimensions of elements are exaggerated orenlarged for clarity of illustration. Like reference numerals refer tolike elements throughout.

FIG. 1 is an exploded perspective view and an appearance schematicallyillustrating a stacked chip device in accordance with an exemplaryembodiment, and FIG. 2 is a cross-sectional conceptual view illustratingan internal pattern of the device of FIG. 1. In other words, FIG. 2 is across-sectional conceptual view cut vertically along an extendeddirection of a conductor pattern in order to show the internalcross-section of a conductor pattern. FIG. 3 is an equivalent circuitdiagram of a unit device in the device of FIG. 1.

Referring to FIGS. 1 and 2, a stacked chip device 10 according to anexemplary embodiment includes a first stack unit B including a pluralityof electrode patterns 110 disposed for each unit device region and acommon electrode pattern 120 formed to be connected to cross the unitdevice regions, and conductor stack units A and C disposed on at leastone side of the top portion and the bottom portion of the first stackunit B and including a plurality of conductor patterns 210 and 310,wherein the conductor patterns 210 and 310 are formed on the pluralityof sheets 200 and 300 and connected vertically through vias 500 formedpenetrating through at least a part of the sheets. In addition, theconductor stack units A and C may include the second stack unit Adisposed on the top portion of the first stack unit B and having theplurality of first conductor patterns 210 and may include a third stackunit C disposed on the bottom portion of the first stack unit B andhaving the plurality of second conductor patterns 310. In other words,the conductor stack units A and C may be disposed only on the topportion or the bottom portion of the first stack unit B, or may bedisposed on both the top and bottom portions. Furthermore, the firststack unit B and the conductor stack units A and C may be stacks 11 inwhich a device having desired properties is implemented. For example,the first stack unit B is a stack in which a plurality of capacitors aredisposed, and the conductor stack units A and C are stacks in which aplurality of inductors are disposed. Sheets used in each of the stackunits are stacked sheets, each of which has each pattern formed thereonand is stacked, and may be a ceramic material or another material, forexample, a semiconducting ceramic sheet, an insulating ceramic sheet, ora varistor material sheet. Furthermore, sheets of an identical materialmay be used in an entire stack or sheets of different materials may beused for each stack unit.

The first stack unit B is a stack in which sheets 101 on which aplurality of patterns 110 respectively disposed for unit device region(indicated with dotted lines) are formed, and sheets 102 and 103 havingcommon electrode patterns 120 formed to be connected to cross the unitdevice region are stacked, and the number of stacked sheets is notlimited. For example, as illustrated in FIG. 1, sheets having the commonelectrode patterns may be stacked only on the top portion or the bottomportion around the sheet 101 having the electrode pattern 110 formedthereon, or sheets 102 and 103 having the common electrode patterns 121and 122 may be respectively stacked on the top and bottom portions.

The plurality of electrode patterns 110 and the common electrodepatterns 121 and 122 are internal electrodes facing each other with asheet in-between, and form a capacitor for each unit device. Theplurality of electrode patterns 110 formed on one sheet include a pairof electrodes 111 and 112 facing each other for each unit device, andthe electrodes 111 and 112 are separated from each other. The electrodepattern 110 is formed to have a predetermined area, and the shapethereof is not particularly limited. Namely, as illustrated, the shapemay be a quadrangle shape or another different shape. The electrodepattern 110 is extended to one side of the sheet 101 inside the sheet101 and exposed externally at the one side of the sheet 101. Forexample, the electrode pattern 110 is extended in a short side directionand exposed at a long side of the sheet 101. The exposed end portion ofthe electrode pattern 110 is connected to an external terminal 600 to bedescribed later. At this point, a width of the exposed one end portionof the plurality of electrode patterns 110 may be smaller than that ofanother end portion, and accordingly, an interval between the endportions of the electrode patterns 110 is increased to expose the endportions. When the exposed end portions are connected to the externalterminal 600, their connections to each other may be restricted. Atleast one of the one end portions of the plurality of electrode patternsmay be positioned deviated from a central line dividing the electrodepattern 110 into two parts, as illustrated in FIG. 5. Accordingly, theinterval between the electrode patterns 110 may be widened and adjusteduniformly. In addition, a capacitance value may be adjusted by adjustingthe areas of the electrode patterns 110.

The common electrode patterns 120 are formed to be connected to crossthe unit device regions divided on the sheet. The common electrodepatterns 120 may function as a common electrode connected for each unitdevice, and may be connected to a common external terminal 613, namely,the ground terminal. The electrode patterns 110 may be connected toother separate external terminals for each unit device, but the commonelectrode pattern may be connected to the common ground. The shape andarea of the common electrode patterns 120 are not particularly limited,and it is sufficient to face the electrode patterns 110 formed at eachunit device region and have overlapping areas. For example, asillustrated in the drawing, the common electrode patterns 120 have aquadrangle shape similar to that of one sheet and are exposed at endportions of the sheet. Namely, the common electrode patterns 120 may beextended along a long side direction of the sheet and exposed externallyat both short sides of the sheet.

The common electrode patterns 120 may be installed separately verticallyfrom the electrode patterns 110 to form a capacitor, and change acapacitance value by adjusting the number of installations and positionsthereof. In addition, the common electrode pattern 120 may includenon-conductor region on at least a part of a portion facing the vias500. The conductor pattern, namely, the first and second conductorpatterns 210 and 310 are formed on the plurality of sheets 200 and 300,the first and second conductor patterns 210 and 310 formed on one sheetare formed across the plurality of unit device regions, and the firstand second patterns 210 and 310 are vertically connected through thevias 500 formed penetrating through at least a part of sheets. Theconductor patterns 210 and 310 are the conductor lines extendedlengthily and extended horizontally and vertically. At this point, theconductor patterns 210 and 310 formed of long lines may function as aninductor having a predetermined resistance value (for example, 50Ω).When the lengths of the conductor patterns 210 and 310 are extended, theresistance values may be increased. For example, the resistance valuemay be adjusted in a range from several ohms to tens of ohms by changingthe number of stacks of the sheets 200 and 300 on which the conductorpatterns 210 and 310 are formed. Furthermore, the conductor patterns 210and 310 may be formed across the unit device regions, not formed foreach unit device region on one sheet. For example, as illustrated inFIG. 1, the first and second conductor patterns 210 and 310 may beformed to cross at least two unit device regions on one sheet. In otherwords, one conductor pattern may be formed on an area corresponding tothe two unit device regions around the first stack unit B. Accordingly,the area and the number that the unit device (one pair of capacitors)occupies on one sheet in the first stack unit B may be different fromthose that the unit device (one inductor) occupies on one sheet in theconductor stacks A and C. For example, 4 electrode patterns (4 pairs ofcapacitors) are disposed in the horizontal direction in the first stackunit B, and conduction patterns (one inductor) are disposed by two inthe horizontal direction and by two in the vertical direction in theconductor pattern units A and C. Accordingly, two among the electrodepatterns on an identical plane are connected to two conductor patterns(namely, the two first conductor patterns 210) on the top portion side,and the other two among the electrode patterns are connected to twoconductor patterns (namely, the two second conductor patterns 310) torespectively form a unit device including a pair of capacitors and oneinductor. At this point, the electrode patterns 110 and the conductorpatterns 210 and 310 are connected through the external terminals 600.In other words, a part (even numbered electrode patterns) of theplurality of electrode patterns 110 and the plurality of first conductorpatterns 210 may be connected to a plurality of first external terminals611, and the remaining part (odd numbered electrode patterns) and theplurality of second conductor patterns 310 may be connected to theplurality of second external terminals 612. At this point, the first andsecond external terminals 611 and 612 may be formed on external sidesurfaces in a long side direction of the stacked chip device, anddisposed alternately along the side surfaces. In addition, when thefirst conductor patterns 210 and the second conductor patterns 310 aredisposed vertically with the first stack unit B in-between, they may bedisposed symmetrically facing each other, and areas that respectivelyoccupied by one of the first conductor patterns 210 and one of thesecond conductor patterns 310 may be identical or similar. At thispoint, the exposed end portion of the first conductor patterns 210 andthe exposed end portion of the second conductor patterns 310 may bedisposed at different positions in the horizontal direction andalternately exposed in the horizontal direction.

The conductor patterns, namely, the first conductor patterns 210 and thesecond conductor patterns 310 may be formed in a spiral type, a meander,a zig-zag type, or the like, formed in plurality (e.g., two) in thehorizontal direction, and connected through the vias 500 formedpenetrating through the plurality of sheets in the vertical direction.Via holes (511 a, 512 a, 521 a, 522 a) penetrating vertically are formedpenetrating through at least a part of sheets on which the conductorpatterns are formed, the internal side of the via holes are filled witha conductor material to form the vias 500, and accordingly the vias 500may electrically or physically connect the conductor patterns on theupper and lower sheets.

The vias 500 may be formed with the minimum number according to theshapes of the conductor patterns 210 and 310, and may be formedseparately or alternately in the horizontal direction and verticaldirection (up and down direction). For example, the vias 500 may includefirst vias 510 vertically connecting the first conductor patterns 210and second vias 520 vertically connecting the second conductor patterns310. Furthermore, the first vias 510 may include first central vias 511formed at central portions of the first conductor patterns 210, andfirst end portion vias 512 formed at end portions of the first conductorpatterns 210, and the second vias 520 may include second central vias521 formed at central portions of the second conductor pattern 310 andsecond end portion vias 522 formed at end portions of the secondconductor patterns 310. Here, a vertical central axis of the firstcentral via 511 and a vertical central axis of the second central via521 may be separately disposed in the horizontal direction, and thefirst end portion vias and the second end portion vias may be separatelydisposed in the horizontal direction. In other words, the first andsecond end portion vias may be formed at different positions in thehorizontal direction. In addition, the first central vias 511 and thefirst end portion vias 512 are formed alternately in the verticaldirection, and the second central vias 521 and the second end portionvias 522 may be formed alternately in the vertical direction.Accordingly, each via 500 may be formed with only one or not be formedwith respect to each conductor pattern of one sheet. In other words, inthe second and third stack units B and C on which the first and secondconductor patterns 210 and 310 are formed, the sheets 206 and 306 of thelowest layers among the sheets 200 and 300 with the conductor patternsformed thereon do not have vias, and the remaining sheets 201 to 205 and301 to 305 respectively have one via formed for each conductor pattern.In addition, the vias are not formed in an overlapped manner at anidentical position in the vertically adjacent sheets, and the first vias510 formed in the second stack unit A positioned on the top portion andthe second vias 520 formed in the third stack unit C positioned on thebottom portion around the first stack unit B are not formed at theidentical position in the horizontal direction. Such a disperseddistribution of vias reduces the vias overlapped in the verticaldirection, and accordingly reduces modification of the vias even whenthe sheets are stacked and compressed. Furthermore, various electricalcharacteristics may be maintained by reducing the modification of thevias.

When including spiral conductor patterns and vias alternately formed atthe central portions and end portions thereof, as illustrated in FIGS. 2and 3, for example, the first conductor patterns 210 are formed by twoon one sheet in the horizontal direction. Each of the first conductorpatterns 210 includes, in the vertical direction, 1-1 conductor patterns211 formed on a first sheet 201, 1-2 conductor patterns 212 formed on asecond sheet 202, 1-3 conductor patterns 213 formed on a third sheet203, 1-4 conductor patterns 214 formed on a fourth sheet 204, 1-5conductor patterns 215 formed on a fifth sheet 205, and 1-6 conductorpatterns 216 formed on a sixth sheet 216. Furthermore, a part of suchpatterns, more specifically, the 1-1 conductor patterns 211 and the 1-6conductor patterns 216 have their end portions exposed externally andconnected to the external terminal 600. In addition, the first centralvias 511 are formed at the central portions of the first conductorpatterns in the first, third, and fifth sheets 201, 203, and 205, andthe first end portion vias 512 are formed at the end portions of thefirst conductor patterns in the second and fourth sheets 202 and 204.Accordingly, the 1-1 to 1-6 conductor patterns 211 to 216 may beconnected through the first central vias 511 and the first end portion512 and form one line structure. The second conductor patterns 310 andthe second vias 520 are formed in the identical structure anddescription thereof is omitted.

In addition, the stacked chip device 10 includes the external terminals600 at external surfaces of the stacks 11 in which the first stack B,the second stack A, and the third stack C are stacked. The commonelectrode patterns 121 and 122 are connected to the common externalterminals 613 at side surfaces in the short side direction of thestacked chip, even-numbered patterns among the electrode patterns 110and the exposed end portions of the first conductor patterns 210 areconnected to first external terminals 611 at the side surfaces in a longside direction of the stacked chip, and odd-numbered patterns among theelectrode patterns 110 and the exposed end portions of the secondconductor patterns 310 are connected to second external terminals 612 atside surfaces in the long side direction of the stacked chip.

The conductor patterns 210 and 310 functioning as an inductor L areconnected to the first and second external terminals 611 and 612 in thestacked chip, an equivalent capacitor C1 is formed by one side electrode111 connected to one side surface terminal of the first and secondexternal terminals 611 and 612 and the common electrode pattern 120connected to the common external terminal 613, and an equivalentcapacitor C2 is formed by another side electrode 112 connected toanother side surface terminal of the first and second external terminals611 and 612 and the common electrode pattern 120 connected to the commonexternal terminal 613. Accordingly, as illustrated in FIG. 3, each unitdevice in the stacked chip device may be manufactured with a π typeinductor-capacitor (LC) filter in which capacitors C1 and C2 arerespectively connected to both sides of the inductor L. Of course, whenthe sheets having the electrode patterns 110 and the common electrodepatterns 120 formed thereon are adopted with sheets of a varistormaterial, a π type inductor-varistor (LV) filter may be manufactured.Furthermore, an equivalent π type ESD filter for preventing staticelectricity may be manufactured by adopting the first and secondexternal terminals 611 and 612 as an input or output stage, and usingthe common external terminal 613 as the ground.

Furthermore, the stacked chip device has a π type structure and issymmetric in horizontal direction and also symmetric in verticaldirection by disposing the second stack unit A and the third stack unitC respectively functioning as an inductor layer on the top and bottomportions around the first stack unit B functioning as a capacitor layer.Accordingly the stacked chip device is undirected and does not need adirection recognition mark, and may perform easily an installation taskat the time of implementing an electronic circuit.

Hereinafter, a manufacturing method of the stacked chip device isbriefly described.

First, molding sheets are prepared for allowing each pattern to beformed thereon and a space between patterns to be separated vertically.In other words, the molding sheets are stacked and then plasticized tobe sheets in the device. The aforementioned sheets is better to beformed in a quadrangle shape, but is not limited hereto and a polygonalshape including a square or a pentagon, a circular shape, or aelliptical shape is possible according to use of a finally manufacturedcomplex stacked chip device. A molding sheet for a desired device ismanufactured. In other words, varistor molding sheets are manufacturedfor manufacturing varistors, capacitor molding sheets are manufacturedfor manufacturing capacitors, and inductor molding sheets aremanufactured for manufacturing inductors. In an exemplary embodiment,varistor molding sheets are used which normally function as a capacitorand the resistance is rapidly changed at the time of overvoltage. To theend, raw material powder of a varistor device commercially available forindustrial use is used or raw material powder is prepared byball-milling a desired composition in which an additive such as Bi₂O₃,CoO, MnO or the like is added to ZnO powder for 24 hours with a solventsuch as water or alcohol. In order to prepare the molding sheets, PVBbased binder, as an additive, is measured by about 6 wt % in contrast tothe raw material powder, dissolved in toluene/alcohol based solvent andthen added to the prepared varistor powder. Then, slurry is manufacturedby milling and mixing for about 24 hours with a small ball mill, and themolding sheets having desired thicknesses is manufactured from theslurry in a doctor blade method, or the like. At this point, the moldingstack sheets having desired thickness may also be manufactured from rawmaterial powder having a capacitor composition and raw material powderhaving a thermistor device composition in the aforementioned method. Inaddition, typical insulating molding sheets may also be used, andsemiconducting molding sheets may be used. Beside, dummy sheets havingferrite patterns printed thereon may be used as the inductor moldingsheets. Alternatively, the inductor molding sheets such as separateferrite sheets may be separately manufactured. In addition, identicalmaterial molding sheets may be used for each stack unit, or anothermaterial molding sheets may also be used. In the exemplary embodiment,varistor molding sheets of identical material are used in entire stackunits. At this point, through-holes penetrating vertically may beinstalled in some molding sheets by using a punching device.

The electrode patterns 110, the common electrode patterns 120 and theconductor patterns 210 and 310 are formed by printing a conductive pastecontaining materials such as Ag, Pt, Pd, Ag—Pd, Ni—Cr, RuO₂ and the likein a screen printing scheme on each of the manufactured molding sheetsby using a screen of a pattern particularly designed. In other words,the electrode patterns 110 and the common electrode patterns 120 areprinted on the molding sheets 101, 102 and 103 to be the first stackunit by using the silk screen and the conductive paste, and theconductor patterns 210 and 310 are printed on the molding sheets 210 to206 and 301 to 306 to be the second and third stack units. At thispoint, the through-holes are filled by burying the conductive paste inthe through-holes.

The molding sheets having each pattern printed thereon are stacked to bestructures of the first to third stack units B, A, and C, as exemplarilyillustrated in FIG. 1. In addition, a dummy molding sheet 411 forprotecting the stack units is stacked on the highest portion. Throughthe stacks, a part of the electrode patterns 110 and the commonelectrode patterns 120 are overlapped and the first and second conductorpatterns 210 and 310 are connected to each other through the filledconductor inside the through-holes, namely, vias.

The stacked stacks are compressed and cut in a proper size. For example,when the unit device is individually cut, the unit device is cut as asingle chip. When a plurality of devices are periodically cut, aplurality of devices are cut as a single chip. In other words, asillustrated in FIG. 1, when cut to allow four unit devices to bedisposed, the four unit devices disposed in parallel may be cut as anarray type single chip. In practical, massive production may bepossible, when patterns formed in one device are formed to appearrepetitively in plurality on one sheet, those sheets are stacked, andthen the stacked sheets are cut in the desired device size, for example,cut as illustrated in FIG. 1,

In order to remove all organic components such as various binders insidethe cut stack, the cut stacks are baked out by heating at about 300° C.and a temperature is increased to burn the cut stacks at a properburning temperature (e.g., about 1100° C.).

The external terminals 600, which are connected to each electrodepattern, the common electrode patterns, and the conductor patternsinside the stack, are installed outside the burnt stacks to complete thestacked chip device. According to the number and positions of electrodeterminals to be formed (the number of external terminals printed on sidesurfaces of the burnt stacks, for example four or one), Ag-paste iscoated on a rubber disc having a groove on a circumferential surface,the rubber disc has a closely contact with a small body and is rotated(dipping operation) to print electrodes. Then external terminals aremanufactured and burnt at a proper temperature. In the abovedescription, one chip formed of four unit devices are exemplified, butit is not limited hereto. In addition, in the above description, eventhough it is exemplified that the conductor patterns of the second andthird stack units on the top and bottom portions of the first stack unitare connected vertically by vias formed penetrating through the sheet,the conductor patterns may be connected in other various schemes.

Hereinafter, description is provided for another embodiment in which thefirst stack B and a stack structure are changed. FIG. 4 is an explodedperspective view and an appearance illustrating a stacked chip deviceaccording to the other embodiment, and FIG. 5 is an exploded perspectiveview illustrating in detail the first stack unit of the device of FIG.4. Most of structures including a basic structure of each stack unit ofthe embodiment are identical and description about the identical part isomitted.

The stacked chip device according to the other embodiment includes afirst stack unit B having a plurality of electrode patterns respectivelydisposed for each unit device region and common electrode patternsformed to be connected to cross the unit device regions, and a conductorstack unit positioned on at least one side of the top and bottomportions of the first stack unit B and including a plurality ofconductor patterns, wherein the conductor patterns are formed on aplurality of sheets, connected vertically through vias formedpenetrating through at least a part of sheets, and the common electrodepatterns include non-conductor regions on at least parts of portionsfacing the vias. Here, the conductor stack unit may include a secondstack unit A positioned on the top portion of the first stack unit B andhaving a plurality of first conductor patterns 210, and a third stackunit C positioned on the bottom portion of the first stack unit B andhaving a plurality of second conductor patterns 310. At least one of thefirst and second conductor patterns 210 and 310 may be connectedvertically through vias formed penetrating through at least some of thesheets.

The common electrode patterns 110 may have a top common electrodepattern 121 formed on the top side of the common electrode pattern 110and a bottom common electrode pattern 122 formed on the bottom side ofthe electrode pattern 110, and may be separated from edges of the sheets102 and 103 to be almost entirely formed, and then both end portionsthereof may be formed to edges of the sheets and exposed externally.Furthermore, the common electrode patterns 120 also includenon-conductor regions 700 at portions in which vias 500 a separatelyinstalled at the top portion or the bottom portion face each other. Forexample, as illustrated in FIG. 5, the top common electrode pattern 121and the bottom common electrode pattern 122 include the non-conductorregions at a portion facing the first vias 510 connecting the firstconductor patterns 210 vertically and at a portion facing the secondvias 520 connecting the second conductor patterns 310 vertically. Inother words, the first non-conductor region 712 is formed at the portionfacing the first end portion vias 512, a second non-conductor region 713is formed at the portion facing the second end portion vias 522, and acentral non-conductor region 711 may be formed at a portion in which afirst central end portion 511 and a second central end portion 521 faceeach other. Here, the non-conductor regions 700 are insulation regionsthrough which electricity is not transmitted, and may include a regionin which parts of the common electrode patterns 121 and 122 are removedand bottom sheets 102 and 103 are exposed. In other words, the commonelectrode patterns may be removed at regions in which the vias 500 andthe common electrode patterns are overlapped. In such a way, when thenon-conductor regions 700 are installed on the common electrode patterns120 in correspondence to the vias 500, even though a stack is compressedto press or modify the vias 500 at the time of manufacturing the stackedchip device, since the non-conductor regions 700 installed on the commonelectrode pattern adjacent to vias 500 are insulating regions, a leakagecurrent or a transient current may be restricted or prevented fromoccurring, or short-circuits between the vias and the common electrodepatterns may be restricted or prevented.

Furthermore, the non-conductor regions 700 may be formed to have thesame size as or greater than that of the vias 500. For example, thediameter of the vias 500 may be in a range from approximately 30 toapproximately 150 μm and at this point, the diameter of thenon-conductor regions 700 may be in a range from approximately 30 toapproximately 300 μm, or in a range from approximately 50 toapproximately 250 μm. Furthermore, a size ratio of the vias 500 and thenon-conductor regions 700 may be in a range from 1 to 10 times, and adiameter ratio of the vias 500 and the non-conductor regions 700 may bein a range from 1.5 to 9 times. When the size of the vias is smallerthan that of the non-conductor regions, the insulation function is notsufficient. When the size of the vias is excessively greater than thatof the non-conductor regions, the insulation function is sufficient andthe area of the common electrode patterns is reduced and the capacitancevalue thereof is reduced.

Furthermore, the stacked chip device of the exemplary embodiment hasdummy sheets 412 and 413 respectively installed between the first andsecond stack units B and A, and between the first and third stack unitsB and C. When the dummy sheets are installed, an interval between eachof the stack units is increased and accordingly interference in-betweencan be restricted or prevented. Of course, by removing the dummy sheetsinstead of adding them, thicknesses of the sheets positioned at theboundaries between the stack units may be increased. In other words,thicknesses of the lowest layer sheet 122 of the first stack unit B andthe lowest layer sheet 206 of the second stack unit A may be allowed tobe thicker, for example, double or more times, than those of othersheets. In addition, the stacked chip device may include the dummy sheet414 even at the lowest portion of the entire stack.

Hereinafter, modification examples in which the structure of thenon-conductor regions is changed are described. FIGS. 6 and 7 areexploded perspective views illustrating in detail a first stack unit ofthe stacked chip device according to a modification example of anexemplary embodiment. FIG. 8 is a cross-sectional view illustrating indetail a non-conductor region in the stacked chip device according to amodification example of the exemplary embodiment. In the stacked chipdevices of the modification examples, most of structures including abasic structure are identical and description about the identical partis omitted.

Referring FIG. 6, the top common electrode pattern 121 includesnon-conductor regions 711 a and 712 at portions facing first vias 510(511 and 512) connecting the first conductor patterns vertically, andnon-conductor regions 711 b and 713 at portions facing second vias 520(521 and 522) connecting the second conductor patterns vertically. Inother words, the non-conductor regions are installed only at portionscorresponding to vias adjacent to each common electrode pattern. Fromthis, while insulation function is sufficient for the modification ofthe vias, the area of the common electrode patterns may be maintainedand reduction of a capacitance value may be restricted.

Referring FIG. 7, the non-conductor regions may be installed not only onthe common electrode patterns but also on electrode patterns. Theelectrode patterns 110 may include the non-conductor regions 720 on atleast parts of portions facing the vias 500. In other words, a part ofthe electric pattern 110 may be removed to expose an insulation sheet101 in the bottom portion. Accordingly, the insulation function formodification of the vias can be more increased. However, since areareduction of the electrode patterns 110 greatly affects the capacitancevalue, it is better to form the non-conductor regions 720 with a smallerarea.

In the aforementioned description with reference to FIG. 8, even thoughthe non-conductor regions are manufactured in a scheme of removing partsof the common electrode patterns or the electrode patterns, otherschemes may be adopted. For example, the non-conductor regions mayinclude an insulation layer covering parts of the common electrodepatterns or the electrode patterns. In other words, the insulation layer730 may be installed which coats an insulation material on the topportion of the common electrode pattern region desired to install thenon-conductor region. At this point, the insulation material may be thesame material as or a different material from that of the sheets.

Besides the examples, various modifications to the non-conductor regionsare possible and the exemplified embodiments and modification examplescan be combined and changed in various schemes.

According to embodiments, via modification can be reduced by adjustingarrangements of vias connecting upper and lower conductor patterns atthe time of manufacturing a stacked chip device. In addition, anon-conduction region is formed in an internal electrode pattern incorrespondence to a region where vias are intensively disposed in thestacked chip device. Accordingly, a short-circuit, a leakage current,and a transient current can be restricted or prevented in the stackedchip device, and originally designed characteristics thereof can beimplemented. In such a way, since electrical characteristics aremaintained and implemented as designed, device reliability can beensured.

Furthermore, since unit devices are disposed symmetrically horizontallyand vertically in the stacked chip device according to embodiments, thestacked chip device can be used as being undirected with respect to thehorizontal and vertical directions. In other words, the stacked chipdevice may be used in implementing an electronic device withoutselection or recognition, and accordingly improve usability withoutcausing miss-insertion in mounting.

Furthermore, desired electrical characteristic values can be easilycontrolled by adjusting arrangement, areas, shapes, the number of stacksor the like of conduction patterns or electrode patterns in the stackedchip device.

Furthermore, the stacked chip device according to embodiments can bemanufactured without a process of inserting a direction recognition markand with a simple manufacturing process without adding other additionalprocesses, thereby improving productivity and reducing a manufacturingcost.

Although the stacked chip device has been described with reference tothe specific embodiments, it is not limited thereto. Therefore, it willbe readily understood by those skilled in the art that variousmodifications and changes can be made thereto without departing from thespirit and scope of the present invention defined by the appendedclaims.

What is claimed is:
 1. A stacked chip device comprising: a first stackunit comprising a plurality of electrode patterns respectively disposedfor a unit device region and common electrode patterns formed to beconnected to cross the unit device regions; a second stack unit disposedon a top portion of the first stack unit and comprising a plurality offirst conductor patterns; and a third stack unit disposed on a bottomportion of the first stack unit and comprising a plurality of secondconductor patterns, wherein the first and second conductor patterns areformed on a plurality of sheets, the first and second conductor patternsformed on one sheet are formed across a plurality of unit deviceregions, and the first and second conductor patterns are connectedvertically through vias formed penetrating through at least some of thesheets.
 2. The stacked chip device of claim 1, wherein the first andsecond conductor patterns are formed on one sheet to cross at least twounit devices, the vias comprises first central vias formed on centralportions of the first conductor patterns, first end portion vias formedon end portions of the first conductor patterns, second central viasformed on central portions of the second conductor patterns, and secondend portions via formed on end portions of the second conductorpatterns, central axes of the first and second central vias areseparated from each other, and the first and second end portion vias areseparately disposed in a horizontal direction.
 3. The stacked chipdevice of claim 2, wherein the first central vias and the first endportion vias are formed alternately in a vertical direction, and thesecond central vias and the second end portion vias are formedalternately in the vertical direction.
 4. The stacked chip device ofclaim 1, further comprising a plurality of first external terminalsconfigured to be connected to parts of the plurality of electrodepatterns and the plurality of first conductor patterns; a plurality ofsecond external terminals configured to be connected to a remaining partof the plurality of electrode patterns and the plurality of secondconductor patterns; and common external terminals connected to thecommon electrode patterns, wherein the first and second externalterminals are disposed alternately.
 5. The stacked chip device of claim1, wherein a width of one exposed end portion of the plurality ofelectrode patterns is narrower than that of another end portion.
 6. Thestacked chip device of claim 5, wherein at least one of the end portionsof the plurality of electrode patterns is deviated from a central lineconfigured to divide the electrode patterns into two parts.
 7. Thestacked chip device of claim 1, wherein the common electrode patternscomprise non-conductor regions on at least parts of portions facing thevias.
 8. A stacked chip device comprising: a first stack unit comprisinga plurality of electrode patterns respectively disposed for a unitdevice region and common electrode patterns formed to be connected tocross the unit device regions; and conductor stack unit configured to bedisposed on at least one side of a top portion and a bottom portion ofthe first stack unit and comprising a plurality of conductor patterns,wherein the conductor patterns are formed on a plurality of sheets andconnected vertically through vias formed penetrating through at leastsome of sheets, and the common electrode patterns comprisesnon-conductor regions on at least parts of portions facing the vias. 9.The stacked chip device of claim 8, wherein a second stack unit disposedon a top portion of the first stack unit and comprising a plurality offirst conductor patterns; and a third stack unit disposed on a bottomportion of the first stack unit and comprising a plurality of secondconductor patterns, wherein at least one of the first and secondconductor patterns are formed on the plurality of sheets, and at leastone of the first and second patterns are connected vertically throughvias formed penetrating through at least some of sheets.
 10. The stackedchip device of claim 9, wherein the common electrode patterns comprise atop common electrode pattern formed on a top portion of the electrodepatterns and a bottom common electrode pattern formed on a bottomportion of the electrode patterns, the top common electrode patterncomprises a non-conductor region on a portion facing a first viaconfigured to connect the first conductor pattern vertically, and thebottom common electrode pattern comprises a non-conductor region on aportion facing a second via configured to connect the second conductorpattern vertically.
 11. The stacked chip device of claim 9, wherein thecommon electrode patterns comprise a top common electrode pattern formedon a top portion of the electrode patterns and a bottom common electrodepattern formed on a bottom portion of the electrode patterns, and thetop common electrode pattern and the bottom common electrode patterncomprise non-conductor regions on a portion facing a first viaconfigured to connect the first conductor patterns vertically and on aportion facing a second via configured to connect the second conductorpatterns vertically.
 12. The stacked chip device of claim 11, whereinthe first vias comprise first central vias formed at central portions ofthe first conductor patterns and first end portion vias formed at endportions of the first conductor patterns, the second vias comprisesecond central vias formed at central portions of the second conductorpatterns and second end portion vias formed at end portions of thesecond conductor patterns, and the first and second end portion vias areseparately disposed at different positions in a horizontal direction.13. The stacked chip device of claim 8, wherein the electrode patternscomprise non-conductor regions on at least parts of portions facing thevias.
 14. The stacked chip device of claim 8, wherein the commonelectrode patterns are formed on a sheet, and the non-conductor regionscomprise regions in which parts of the common electrode patterns areremoved and the sheet is exposed.
 15. The stacked chip device of claim8, wherein the non-conductor regions comprise insulation layersconfigured to cover parts of the common electrode patterns.
 16. Thestacked chip device of claim 8, wherein the non-conductor regions areformed with a size that is the same as or greater than that of the vias.